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Design and performances of a compensated mean-timer

Abstract : An integrated mean-timer has been designed. This circuit integrates a compensation system in order to minimize thermal drift and process variations. This circuit designed in BiCMOS 0.8 mu m integrates input and output ECL translators. The drift cancellation system is based on a regulated delay line controlled by a PLL. The PLL circuit can be disconnected and an external control voltage can be used. The circuit can also run without any cancellation system. In the last part, a sub-delay resolution system is discussed.
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http://hal.in2p3.fr/in2p3-00005874
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Submitted on : Thursday, August 24, 2000 - 1:16:43 PM
Last modification on : Wednesday, May 19, 2021 - 4:54:01 PM

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  • HAL Id : in2p3-00005874, version 1

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Daniel Dzahini, J. Pouxe, O. Rossetto. Design and performances of a compensated mean-timer. IEEE 1999 Nuclear Science Symposium and Medical Imaging Conference, Oct 1999, Seattle, United States. pp.839-843. ⟨in2p3-00005874⟩

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