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A 16-channel digital TDC chip

Abstract : A 16-channel digital TDC chip has been built for the DIRC Cherenkov counter of the BaBar experiment at the SLAC B-factory (Stanford, USA). The binning is 0.5 ns, the conversion time 32 ns and the full-scale 32 mus. The data driven architecture integrates channel buffering and selective readout of data falling within a programmable time window. The time measuring scale is constantly locked to the phase of the (external) clock. The linearity is better than 80 ps rms. The dead time loss is less than 0.1% for incoherent random input at a rate of 100 khz on each channel. At such a rate the power dissipation is less than 100 mw. The die size is 36 mm2.
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Contributor : Jean-Michel Levy <>
Submitted on : Thursday, October 12, 2000 - 4:40:15 PM
Last modification on : Friday, April 10, 2020 - 5:04:06 PM


  • HAL Id : in2p3-00006544, version 1


P. Bailly, J. Chauveau, J F. Genat, J F. Huppert, H. Lebbolo, et al.. A 16-channel digital TDC chip. Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, Elsevier, 1999, 433, pp.432-437. ⟨in2p3-00006544⟩



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