A low power, and low signal 5-bit 25 Msamples/s pipelined ADC for monolithic active pixels

J. Bouvier 1 M. Dahoumane 1 D. Dzahini 1 J.Y. Hostachy 1 E. Lagorio 1 O. Rossetto 1 H. Ghazlane Dominique Dallet 2
2 Conception
IXL - Laboratoire d'études de l'intégration des composants et systèmes électroniques
Abstract : For CMOS monolithic active pixels sensor readout, we developed a 5 bit low power analog to digital converter using a pipelined architecture. A non-resetting sample and hold stage is included to amplify the signal by a factor of 4. Due to the very low level of the incoming signal, this first stage compensates both the amplifier offset effect and the input common mode voltage dispersion. The converter consists of three 1.5 bit sub-ADC and a 2 bit flash. We present the results of a prototype, comprising of eight ADC channels. The maximum sampling rate is 25MS/s. The total DC power consumption is 1.7mW/channel on a 3.3V supply voltage recommended for the process. But at a reduced 2.5V supply, it consumes only 1.3mW. The size for each ADC channel layout is only 43µm*1.43mm. This corresponds to the pitch of two columns of pixels, each one would be 20µm wide. The full analog part of the converter can be quickly switched to a standby idle mode in less than 1µs; thereby reducing the power dissipation to a ratio better than 1/1000. This fast power fall is very important for the ILC vertex detector because it renders the total power dissipation directly proportional to the beam low duty cycle.
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J. Bouvier, M. Dahoumane, D. Dzahini, J.Y. Hostachy, E. Lagorio, et al.. A low power, and low signal 5-bit 25 Msamples/s pipelined ADC for monolithic active pixels. 2006 Nuclear Science Symposium, Medical Imaging Conference, 2006, San Diego, California, United States. pp.375-379. ⟨in2p3-00119517⟩

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