A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors

M. Dahoumane 1 D. Dzahini 1 J. Bouvier 1 E. Lagorio 1 J.Y. Hostachy 1 O. Rossetto 1 H. Ghazlane Dominique Dallet 2
1 LPSC - Laboratoire de Physique Subatomique et de Cosmologie
2 Conception
IXL - Laboratoire d'études de l'intégration des composants et systèmes électroniques
Abstract : A 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35μm CMOS technology. A non-resetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of a 2.5 bit pipeline stage followed by a 2 bit flash stage. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1μs. The size for the layout is 80μm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20μm wide.
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Submitted on : Wednesday, November 14, 2007 - 8:59:58 AM
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M. Dahoumane, D. Dzahini, J. Bouvier, E. Lagorio, J.Y. Hostachy, et al.. A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors. Topical Workshop on Electronics for Particle Physics (TWEPP-07), Sep 2007, Prague, Czech Republic. pp.326-331. ⟨in2p3-00186598⟩

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