Conference papers
A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors
Abstract : A 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35μm CMOS technology. A non-resetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of a 2.5 bit pipeline stage followed by a 2 bit flash stage. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1μs. The size for the layout is 80μm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20μm wide.
Cited literature [9 references]
http://hal.in2p3.fr/in2p3-00186598
Contributor : Emmanuelle Vernay <>
Submitted on : Wednesday, November 14, 2007 - 8:59:58 AM
Last modification on : Tuesday, February 9, 2021 - 4:18:01 PM
Long-term archiving on: : Monday, April 12, 2010 - 1:47:33 AM
Contributor : Emmanuelle Vernay <>
Submitted on : Wednesday, November 14, 2007 - 8:59:58 AM
Last modification on : Tuesday, February 9, 2021 - 4:18:01 PM
Long-term archiving on: : Monday, April 12, 2010 - 1:47:33 AM
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ADC_DS_4b.pdf
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