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A CMOS 130nm Evaluation Digitizer Chip for Silicon Strips Readout

Abstract : A CMOS 130nm evaluation chip intended to read Silicon strip detectors at the ILC has been designed and successfully tested. Optimized for a detector capacitance of 10 pF, it includes four channels of charge integration, pulse shaping, a 16-deep analogue sampler triggered on input analogue sums, and parallel analogue to digital conversion. Tests results of the full chain are reported, demonstrating the behaviour and performance of the full sampling process and analogue to digital conversion. Each channel dissipates less than one milli-Watt static power.
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Contributor : Dominique Girod <>
Submitted on : Wednesday, November 14, 2007 - 9:53:34 AM
Last modification on : Monday, December 14, 2020 - 9:53:08 AM
Long-term archiving on: : Monday, April 12, 2010 - 2:08:24 AM


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  • HAL Id : in2p3-00187255, version 1


W. da Silva, J. David, M. Dhellot, D. Fougeron, J.-F. Genat, et al.. A CMOS 130nm Evaluation Digitizer Chip for Silicon Strips Readout. Topical Workshop on Electronics for Particle Physics (TWEPP-07), Sep 2007, Prague, Czech Republic. ⟨in2p3-00187255⟩



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