A 35 mW 12 Bits 25 MS/s Pipelined Analog to Digital Converter

J. Bouvier 1 M. Dahoumane 1 D. Dzahini 1 L. Gallin-Martel 1 J.Y. Hostachy 1 E. Lagorio 1 O. Rossetto 1 H. Ghazlane Dominique Dallet 2
2 Conception
IXL - Laboratoire d'études de l'intégration des composants et systèmes électroniques
Abstract : The design of full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with the analog to digital converter. We present here a 12 bits 25 MHz analog to digital converter using the pipe line architecture. Its' first stage is a charge redistribution sample and hold, then follow ten 1.5 bit sub-ADC and finally a 2 bit flash. A CMOS 0.35µ process is used, and the dynamic range to cover is 1 V. The analog part of the converter can be quickly switched (less than 1µs) to a standby mode that reduces the DC power dissipation by a ratio of 1/1000. The size of the converter's layout including the digital correction stage is only 1.7mm*0.6mm, and the power dissipation expected is 35mW.
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Submitted on : Wednesday, November 14, 2007 - 5:24:41 PM
Last modification on : Thursday, July 5, 2018 - 11:12:07 PM

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  • HAL Id : in2p3-00187563, version 1

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J. Bouvier, M. Dahoumane, D. Dzahini, L. Gallin-Martel, J.Y. Hostachy, et al.. A 35 mW 12 Bits 25 MS/s Pipelined Analog to Digital Converter. 2007 IEEE Nuclear Science Symposium and Medical Imaging Conference, Oct 2007, Honolulu, United States. pp.2489-2493. ⟨in2p3-00187563⟩

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