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A Low Power Multi-Channel Single Ramp ADC With Up to 3.2 GHz Virtual Clock

Abstract : During the last decade, ADCs using single ramp architecture have been widely used in integrated circuits dedicated to nuclear science applications. These types of converters are actually very well suited for low power, multi-channel applications. Moreover their wide dynamic range and their very good differential non-linearity are perfectly matched to spectroscopy measurement. Unfortunately, their use is limited by their long conversion time, itself limited by their maximum clock frequency. A new architecture is described in this paper. It permits speeding up the conversion time of the traditional ramp ADC structures by a factor of 32 while keeping a low power consumption. Measurement results on a 4-channel, 12-bit prototype using a 3.2 GHz virtual clock are then presented in detail, showing excellent performances of linearity and noise.
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http://hal.in2p3.fr/in2p3-00308947
Contributor : Sabine Starita <>
Submitted on : Monday, August 4, 2008 - 4:18:34 PM
Last modification on : Wednesday, September 16, 2020 - 4:13:40 PM
Long-term archiving on: : Thursday, June 3, 2010 - 5:44:13 PM

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E. Delagnes, D. Breton, F. Lugiez, R. Rahmanifard. A Low Power Multi-Channel Single Ramp ADC With Up to 3.2 GHz Virtual Clock. IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2007, 54, pp.1735-1742. ⟨10.1109/TNS.2007.906170⟩. ⟨in2p3-00308947⟩

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