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Poster communications

Design and measurements of SEU tolerant latches

Abstract : The single event upset (SEU) tolerance of various latch designs in 0.13um CMOS technology has been studied by both measurement and simulation. The aim of this work is to optimize the design for critical registers on the next generation pixel readout chip for ATLAS upgrades (denominated FE-I4). Results form irradiations with 24 GeV protons will be presented and compared to previous values obtained with heavy ions. Layout effects will be discussed and quantified along with other design considerations
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Poster communications
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Contributor : Danielle Cristofol Connect in order to contact the contributor
Submitted on : Wednesday, September 24, 2008 - 9:01:13 AM
Last modification on : Tuesday, October 19, 2021 - 10:50:13 PM


  • HAL Id : in2p3-00324089, version 1



M. Menouni, D. Arutinov, M. Barbero, R. Beccherle, P. Breugnon, et al.. Design and measurements of SEU tolerant latches. TWEEP-08 Topical Workshop on Electronics for Particle Physics, Sep 2008, Naxos, Greece. pp.402-405, 2008. ⟨in2p3-00324089⟩



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