Skip to Main content Skip to Navigation
Conference papers

Optimization of pipelined ADC architecture for Monolithic Active Pixel Sensors

M. Dahoumane 1 D. Dzahini 1 J. Bouvier 1 E. Lagorio 1 O. Rossetto 1 J.Y. Hostachy 1 H. Ghazlane Dominique Dallet 2
2 Conception
IXL - Laboratoire d'études de l'intégration des composants et systèmes électroniques
Abstract : For CMOS monolithic active pixels sensor readout, we developed two architectures of low power and low signal pipelined analog to digital converter (ADC) which are 5bit, 25 MS/s pipelined ADC and 4 bit, 50 MS/s double sampling ADC. Both architectures include a non-resetting sample and hold stage to amplify the signal by a factor of 4. Due to the very low level of the incoming signal, this first stage compensates both of the amplifier offset effect and the input common mode voltage dispersion. The traditional pipelined ADC consists of three 1.5 bit sub-ADC and a 2 bit flash. And the double sampling architecture consists of one double channel 2.5bit stage followed by a 2 bit flash stage. We present the results of prototypes, made of eight ADC channels. A comparative study is done. For the above designs, the full analog part of the converter can be quickly switched to a standby idle mode in less than 1μs; thus reducing the power dissipation to a ratio better than 1/1000. This fast shutdown is very important for the ILC vertex detector as the total DC power dissipation becomes directly proportional to the low beam duty cycle.
Complete list of metadatas
Contributor : Emmanuelle Vernay <>
Submitted on : Monday, October 6, 2008 - 10:37:09 AM
Last modification on : Friday, July 3, 2020 - 4:39:13 PM


  • HAL Id : in2p3-00326829, version 1


M. Dahoumane, D. Dzahini, J. Bouvier, E. Lagorio, O. Rossetto, et al.. Optimization of pipelined ADC architecture for Monolithic Active Pixel Sensors. 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), 2007, Marrakech, Morocco. pp.665-668. ⟨in2p3-00326829⟩



Record views