Skip to Main content Skip to Navigation
Conference papers

A 23-24 GHz low power frequency synthesizer in 0.25 μm SiGe

O. Mazouffre 1 H. Lapouyade J.B. Begueret A. Cathelin D. Belot P. Hellmuth 2 Y. Deval 1
1 IMS - Laboratoire de l'intégration, du matériau au système
2 CENBG - Centre d'Etudes Nucléaires de Bordeaux Gradignan
Abstract : This paper presents the design and the experimental measurements of a 24 GHz fully integrated fractional PLL, for ISM band, with a new low power prescaler. This circuit is implemented in a 0.25 mu m SiGe:C process from STMicroelectronics (BiCMOS7RF). The PLL power dissipation is 170 mW and fulfills a 23.7 to 24.9 GHz frequency locking range, while exhibiting a phase noise of -100 dBc/Hz at 100 KHz from the carrier. The simulated PLL unity-gain bandwidth is 36 MHz, with a phase margin of 54 degrees. The PLL uses a new latch-based prescaler (SRO) which exhibits a power dissipation of 0.68 GHz/mW
Document type :
Conference papers
Complete list of metadatas
http://hal.in2p3.fr/in2p3-00370534
Contributor : Virginie Mas <>
Submitted on : Tuesday, March 24, 2009 - 3:29:43 PM
Last modification on : Wednesday, October 9, 2019 - 9:30:02 PM

Identifiers

  • HAL Id : in2p3-00370534, version 1

Collections

IN2P3 | CENBG | CNRS | IMS-BORDEAUX | IMS-BORDEAUX-FUSION

Citation

O. Mazouffre, H. Lapouyade, J.B. Begueret, A. Cathelin, D. Belot, et al.. A 23-24 GHz low power frequency synthesizer in 0.25 μm SiGe. 13th European Gallium Arsenide and Other Compound Semiconductors Application Symposium, Oct 2005, Paris, France. pp.533-536. ⟨in2p3-00370534⟩

Export

BibTeX TEI DC DCterms EndNote

Share

Metrics

Record views

168