The aim of the NEMO collaboration is to investigate neutrino-less double-beta decay. This research is one of the principal topics in neutrino physics and it can play a particularly interesting role in providing the answers to questions on the nature of the neutrino. Optimized running in double-beta mode in the SuperNEMO experiment implies working without hardware trigger and with absolute time measurements. To fulfil this requirement, a time stamp system is needed for the calorimeter front-end electronics. The SNATS chip is designed to provide both a high resolution of 70ps RMS and a large dynamic range of 53 bits. The architecture is based on the association of delay locked loops (DLL) and of a digital counter which are synchronized to a 160 MHz external clock. A 16-channel prototype has been designed in AMS 0.35 m CMOS technology. The chip contains 8 single ended DLL and a common counter. Each DLL, shared between 2 channels, includes 32 delay elements giving a binning of 200 ps. The characteristic of the delay cells offers a low slope of 0.15ps /mV at a typical frequency of 160 MHz which minimizes the jitter at the end of the DLL. A 48-bit GRAY counter, running at 200MHz, is employed for coarse conversion and used to measure a time range of about 20 days. In order to avoid any junction error due to the phase difference between the DLL and the counter, SNATS makes use of an original solution. It is based on a synchronizer whose principle consists in generating a signal delayed in function of the relative position of the hit arrival within the clock period. This permits always latching the state of the counter when its outputs are in adequate relation with the DLL. The silicon area is then drastically reduced when compared to a twocounter option. Concerning the performances, a Differential Non Linearity of about ±0.2 LSB has been measured, as well as an Integral Non Linearity about ±1.3 LSB. The static power dissipation is of about 380mW.