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A digitally calibrated 12 bits 35 MS/s pipelined ADC with a 32 input multiplexer for CALICE integrated readout

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http://hal.in2p3.fr/in2p3-00423557
Contributor : Emmanuelle Vernay <>
Submitted on : Monday, October 12, 2009 - 9:26:36 AM
Last modification on : Wednesday, May 19, 2021 - 4:54:01 PM

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  • HAL Id : in2p3-00423557, version 1

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Citation

F. Rarbi, Daniel Dzahini, L. Gallin-Martell, J.Y. Hostachy. A digitally calibrated 12 bits 35 MS/s pipelined ADC with a 32 input multiplexer for CALICE integrated readout. Topical Workshop on Electronics for Particle Physics (TWEPP-09), Sep 2009, Paris, France. Cern, 2009-006, pp.533-538, 2009. ⟨in2p3-00423557⟩

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