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Conference papers
Design of high dynamic range digital to analog converters for calibration of the CALICE readout electronics
Abstract : The ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to calibration. We present two versions of DAC with respectively 12 and 14 bits, designed in a CMOS 0.35μm process. Both are based on segmented arrays of switched capacitors controlled by a Dynamic Element Matching (DEM) algorithm. A full differential architecture is used, and the amplifiers can be turned into a standby mode reducing the power dissipation. The 12 bit DAC features an INL lower than 0.3 LSB at 5MHz, and dissipates less than 7mW. The 14 bit DAC is an improved version of the 12 bit design.
http://hal.in2p3.fr/in2p3-00423558
Contributor : Emmanuelle Vernay <>
Submitted on : Monday, October 12, 2009 - 9:31:11 AM
Last modification on : Wednesday, May 19, 2021 - 4:54:01 PM
Contributor : Emmanuelle Vernay <>
Submitted on : Monday, October 12, 2009 - 9:31:11 AM
Last modification on : Wednesday, May 19, 2021 - 4:54:01 PM