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A 12-bit 35MS/s Pipelined ADC with a dynamic element matching

Abstract : A low power 12 bits analog to digital converter is a critical part of a fully integrated readout system for the next ILC ECAL. We present here a new design of 12-bit ADC up to 35-MS/s using a pipelined architecture in a CMOS 0.35 m process. The first front-end stage of 2.5 bits includes an efficient dynamic element matching scheme permitting to average its gain errors. The back-end converter is a set of seven 1.5 bit stages followed by a 3 bit full flash. The dynamic range covered is 2V. The analog part of the converter can be quickly (in a couple of s) switched to a standby mode that reduces the DC power dissipation. The size of this converters layout including the output pads is 1.4mm*1.3mm, and the total power dissipation is only 45mW.
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Submitted on : Monday, October 26, 2009 - 9:09:15 AM
Last modification on : Monday, July 20, 2020 - 9:18:24 AM


  • HAL Id : in2p3-00426389, version 1




F. Rarbi, D. Dzahini, L. Gallin-Martel. A 12-bit 35MS/s Pipelined ADC with a dynamic element matching. 2009 IEEE Nuclear Science Symposium and Medical Imaging Conference, Oct 2009, Orlando, United States. pp.47-52. ⟨in2p3-00426389⟩



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