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A low power 5MS/s 14 bit switched capacitors digital to analog converter

Abstract : The ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to the calibration. We present a 14 bit DAC, designed in a CMOS 0.35 μm process and based on segmented arrays of switched capacitors controlled by a Dynamic Element Matching (DEM) algorithm. This DAC features an INL lower than 0.5 LSB at 5 MHz, and dissipates less than 7 mW.
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http://hal.in2p3.fr/in2p3-00488840
Contributor : Emmanuelle Vernay <>
Submitted on : Thursday, June 3, 2010 - 10:17:09 AM
Last modification on : Monday, July 20, 2020 - 9:18:27 AM

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  • HAL Id : in2p3-00488840, version 1

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Citation

L. Gallin-Martel, D. Dzahini, F. Rarbi, O. Rossetto. A low power 5MS/s 14 bit switched capacitors digital to analog converter. IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), Jun 2010, Grenoble, France. pp.240-243. ⟨in2p3-00488840⟩

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