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The design for test architecture in digital section of the ATLAS FE-I4 chip

Abstract : This paper describes an original Design-for-Test (DfT) architecture implemented in the ATLAS FE-I4 pixel readout System-on-Chip (Soc) to accommodate the higher quality demands of future generation LHC detectors. To ensure that the highest possible number of fault-free devices is used for the detector construction, the so-called production test to detect faulty devices after the manufacturing has to be executed. For that reason, we devised a straightforward and effective DfT circuitry inside the digital part of the FE-I4 that will enable high fault coverage of potential structural faults while maintaining the performance and area penalties of the entire design negligible.
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http://hal.in2p3.fr/in2p3-00562090
Contributor : Sabine Starita <>
Submitted on : Wednesday, February 2, 2011 - 5:03:10 PM
Last modification on : Saturday, October 3, 2020 - 3:12:56 AM

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V. Zivkovic, J.-D. Schipper, R. Kluit, M. Garcia-Sciveres, A. Mekkaoui, et al.. The design for test architecture in digital section of the ATLAS FE-I4 chip. Topical Workshop on Electronics for Particle Physics 2010, TWEPP 2010, Sep 2010, Aachen, Germany. pp.C01090, ⟨10.1088/1748-0221/6/01/C01090⟩. ⟨in2p3-00562090⟩

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