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Hardware Implementation of an ADC Error Compensation Using Neural Networks

Abstract : A compensation technique for Analog-to-Digital Converter (ADC) based on a neural network is proposed. The implementation is done both in software and in a hardware description language. The latter is targeted for a massively parallel ASIC. The training of the neural network is done by learning a Look Up Table generated by processing the output of the ADC for sine waves inputs. Then, the effective number of bits (ENOB) is computed over a large range of frequencies for the raw data of a 100MS/s ADC and for the compensated data. These results are used to compare various neural network architecture and the effects of the approximations made for the hardware implementation.
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http://hal.in2p3.fr/in2p3-00612913
Contributor : Jeanine Pellet <>
Submitted on : Monday, August 1, 2011 - 3:10:04 PM
Last modification on : Tuesday, April 20, 2021 - 12:00:09 PM

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  • HAL Id : in2p3-00612913, version 1

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Hervé Chanal. Hardware Implementation of an ADC Error Compensation Using Neural Networks. International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design and IEEE 2011 ADC Forum, Jun 2011, Ovieto, Italy. 6 p. ⟨in2p3-00612913⟩

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