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The FE-I4 pixel readout system-on-chip resubmission for the insertable B-Layer project

Abstract : The FE-I4 is a new pixel readout integrated circuit designed to meet the requirements of ATLAS experiment upgrades. The first samples of the FE-I4 engineering run (called FE-I4A) delivered promising results in terms of the requested performances. The FE-I4 team envisaged a number of modifications and fine-tuning before the actual exploitation, planned within the Insertable B-Layer (IBL) of ATLAS. As the IBL schedule was pushed significantly forward, a quick and efficient plan had to be devised for the FE-I4 redesign. This article will present the main objectives of the resubmission, together with the major changes that were a driving factor for this redesign. In addition, the top-level verification and test efforts of the FE-I4 will also be addressed.
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http://hal.in2p3.fr/in2p3-00705895
Contributor : Sabine Starita <>
Submitted on : Friday, June 8, 2012 - 2:42:28 PM
Last modification on : Saturday, October 3, 2020 - 3:13:50 AM

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V. Zivkovic, J.D. Schipper, M. Garcia-Sciveres, A. Mekkaoui, M. Barbero, et al.. The FE-I4 pixel readout system-on-chip resubmission for the insertable B-Layer project. Topical Workshop on Electronics for Particle Physics - TWEPP-11, Sep 2011, Vienna, Austria. pp.C02050, ⟨10.1088/1748-0221/7/02/C02050⟩. ⟨in2p3-00705895⟩

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