Abstract : The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches where layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. For the future pixel readout design, a prototype chip containing 512 pixels is implemented in a 65 nm CMOS process. SEU tolerant latches are implemented for the pixel configuration and the SEU tolerance is under test and evaluation.