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Conference papers
SEU tolerant memory design for the ATLAS pixel readout chip
M. Menouni
1
D. Arutinov
M. Backhaus
M. Barbero
1
R. Beccherle
P. Breugnon
1
L. Caminada
S. Dube
G. Darbo
J. Fleury
D. Fougeron
1
M. Garcia-Sciveres
F. Gensolen
1
D. Gnani
L. Gonella
V. Gromov
T. Hemperek
F. Jensen
M. Karagounis
R. Kluit
H. Krueger
A. Kruth
Y. Lu
A. Mekkaoui
A. Rozanov
1
J.-D Schipper
V. Zivkovic
1
CPPM - Centre de Physique des Particules de Marseille (163, avenue de Luminy - Case 902 - 13288 Marseille cedex 09 - France)
- AMU - Aix Marseille Université : UMR7346 / UMR6550 / UMR6450 / URA6450 (Aix-Marseille Université Jardins du Pharo 58 Boulevard Charles Livon 13284 Marseille cedex 7 - France)
- IN2P3 - Institut National de Physique Nucléaire et de Physique des Particules du CNRS (France)
- CNRS - Centre National de la Recherche Scientifique : UMR7346 / UMR6550 / UMR6450 / URA6450 (France)
Abstract : The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. To prepare for the new pixel readout chip planned for the future upgrades, a prototype chip containing 512 pixels has been designed in a 65 nm CMOS process and a new approach is adopted for SEU tolerant latches. Results in terms of SEU and TID tolerance are presented.
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Conference papers
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http://hal.in2p3.fr/in2p3-00800250
Contributor : Danielle Cristofol <>
Submitted on : Wednesday, March 13, 2013 - 2:50:57 PM
Last modification on : Monday, March 29, 2021 - 3:22:06 PM
Contributor : Danielle Cristofol <>
Submitted on : Wednesday, March 13, 2013 - 2:50:57 PM
Last modification on : Monday, March 29, 2021 - 3:22:06 PM
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- HAL Id : in2p3-00800250, version 1
- DOI : 10.1088/1748-0221/8/02/C02026
Citation
M. Menouni, D. Arutinov, M. Backhaus, M. Barbero, R. Beccherle, et al.. SEU tolerant memory design for the ATLAS pixel readout chip. Topical Workshop on Electronics for Particle Physics 2012 (TWEPP12), Sep 2012, Oxford, United Kingdom. pp.C02026, ⟨10.1088/1748-0221/8/02/C02026⟩. ⟨in2p3-00800250⟩
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