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Results of 65nm pixel readout chip demonstrator array

Abstract : We have explored the use of the 65 nm CMOS technology node for pixel readout. A demonstrator 500-pixel matrix containing analog front ends only (no complex functionality), was designed and fabricated in Summer 2011, and irradiated with protons in Dec. 2011 and May 2012. We present the design and measurement results for this prototype.
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http://hal.in2p3.fr/in2p3-00800268
Contributor : Danielle Cristofol <>
Submitted on : Wednesday, March 13, 2013 - 3:00:53 PM
Last modification on : Tuesday, March 30, 2021 - 3:20:23 AM

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  • HAL Id : in2p3-00800268, version 1

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A. Mekkaoui, M. Menouni, D. Gnani, M. Garcia-Sciveres. Results of 65nm pixel readout chip demonstrator array. TWEPP 2012 Topical Workshop on Electronics for Particle Physics, Sep 2012, Oxford, United States. ⟨in2p3-00800268⟩

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