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Poster communications

SPECS MASTER PCIExpress System

D. Charlet 1
1 Sce Electronique
LAL - Laboratoire de l'Accélérateur Linéaire
Abstract : The LHCb sub-detector electronics are organized around the detector in chassis or on individual boards, which requires configuration access to load or read different types of information. The experiment requires a configuration bus, capable to communicate properly on a copper line for a distance of over 100 meters, with a unique master, located in the control room which is not exposed to radiation, and up to 32 slaves implemented close to the detector electronics boards, working in a radiation sensitive environment. A complete Serial Protocol for Experiment Configuration System (SPECS) system was developed in 2005 based on PCI boards and detector mezzanines. The protocol requires 4 differential copper links over a standard Ethernet CAT6 cable using BLVDS technology with a transfer rate of 10Mbit/s in each direction. For PC obsolescence reasons, a new SPECS-MASTER (SPECSPCIE) is developed for the upgrade, based on the XTCA standard (full-size double-width). The SPECSPCIE board can be housed in XTCA chassis or in individual boxes. For this configuration, a COMExpress module provides all the link interfaces: Ethernet, PCIexpress, and JTAG. The board's core is the new ARRIA V GX FPGA family which implemented hard PCIexpress IP and transceivers at 3.125 Gbps which allow direct connections with the serial links: 1Gb Ethernet and PCIexpress 4X GEN 2. The board has been designed as aversatile system, it integrates 16 SPECS-MASTER with individual drivers with discrete pole zero compensation and per-emphasis to allow a transfer length of up to 120m. It also include a mezzanine HSMC connector for future development. An 8bits microcontroller manages the XTCA startup sequence and the communication with the chassis controller (MCH) using the IPMB bus, and also the programmable power supervisor by I2C bus. A clock generator and jitter cleaner chip is implemented onboard and allows wide clock frequencies (40Khz to 1.5Ghz) with very low jitter performance (.35ps RMS). This last one is configured by a SPI bus which is controlled by an on-chip NIOS CPU. To allow complex systems with easy programming an embedded uLinux system is implemented. With this configuration, we manage the Ethernet TCP/IP protocol. CPU communication is performed via PCIexpress or Ethernet link. The FPGA configuration is achieved by serial EEPROM, and reconfiguration by JTAG or by CvP (PCIexpress capability). Software libraries are available to use the SPECS System. One low level library allows users to access the master registers and to prepare and send SPECS frames to communicate with the electronics using the different modes available (I2C, JTAG, DMA Bus, Parallel Bus). One high level library interfaces all commonly used functionalities to write or read data directly to the electronics.
Complete list of metadatas

http://hal.in2p3.fr/in2p3-00995658
Contributor : Sabine Starita <>
Submitted on : Friday, May 23, 2014 - 3:07:40 PM
Last modification on : Wednesday, October 14, 2020 - 3:56:55 AM

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  • HAL Id : in2p3-00995658, version 1

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IN2P3 | LAL | CNRS

Citation

D. Charlet. SPECS MASTER PCIExpress System. RT2014 - 19th Real-Time Conference, May 2014, Nara, Japan. ⟨in2p3-00995658⟩

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