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Poster communications

PEALL4: A 4-channel, 12-bit, 40-MSPS, Power Efficient and Low Latency SAR ADC

F. Rarbi 1 D. Dzahini 1 L. Gallin-Martel 1 J. Bouvier 1 M. Zeloufi 1 B. Trocmé 1 C. Gabaldon-Ruiz 1
1 LPSC - Laboratoire de Physique Subatomique et de Cosmologie
Abstract : The PEALL4 chip is a Power Efficient And Low Latency 4-channels, 12-bit and 40-MSPS successive approximation register (SAR) ADC. It was designed featuring a very short latency time in the context of ATLAS Liquid Argon Calorimeter phase I upgrade. Moreover this design could be a good option for ATLAS phase II and other High Energy Physics (HEP) projects. The full functionality of the converter is achieved by an embedded high-speed clock frequency conversion generated by the ADC itself. The design and testing results of the PEALL4 chip implemented in a commercial 130nm CMOS process are presented. The size of this 4-channel ADC with embedded voltage references and sLVS output serializer is 2.8x3.4 mm2. The chip presents a short latency time less than 25 ns defined from the very beginning of the sampling to the last conversion bit made available. A total power consumption below 27mW per channel is measured including the reference buffer and the sLVS serializer.
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Poster communications
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http://hal.in2p3.fr/in2p3-01067743
Contributor : Emmanuelle Vernay <>
Submitted on : Wednesday, September 24, 2014 - 8:40:10 AM
Last modification on : Tuesday, February 9, 2021 - 4:18:02 PM

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F. Rarbi, D. Dzahini, L. Gallin-Martel, J. Bouvier, M. Zeloufi, et al.. PEALL4: A 4-channel, 12-bit, 40-MSPS, Power Efficient and Low Latency SAR ADC. Topical Workshop on Electronics for Particle Physics (TWEPP 2014), Sep 2014, Aix en Provence, France. Journal of Instrumentation, 10, pp.C01012, 2015, ⟨10.1088/1748-0221/10/01/C01012⟩. ⟨in2p3-01067743⟩

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