A 12 bit 40 MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LAr calorimeter readout

Abstract : We present a SAR ADC with a generalized redundant search algorithm offering the flexibility to relax the requirements on the DAC settling time. The redundancy also allows a digital background calibration, based on a code density analysis, to compensate for the capacitor mismatch effects. The total number of capacitors used in this architecture is limited to one half of the one in a classical SAR design. Only 211 unit capacitors were necessary to reach 12 bit resolution, and the switching algorithm is intrinsically monotonic. The design is fully differential featuring 12 bit 40 MS/s in a CMOS 130 nm 1P8M process.
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Communication dans un congrès
19th International Conference on Circuits, Systems, Communications and Computers (CSCC 2015), Jul 2015, Zakynthos Island, Greece. Recent Advances in Circuits Proceedings of the 19th International Conference on Circuits (part of CSCC '15) Zakynthos Island, Greece July 16‐20, 2015, Recent Advances in Electrical Engineering Series, 51, pp.129-132, 2015
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http://hal.in2p3.fr/in2p3-01179604
Contributeur : Emmanuelle Vernay <>
Soumis le : jeudi 23 juillet 2015 - 08:36:00
Dernière modification le : mardi 22 mai 2018 - 21:48:11

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  • HAL Id : in2p3-01179604, version 1

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M. Zeloufi, D. Dzahini, F.E. Rarbi. A 12 bit 40 MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LAr calorimeter readout. 19th International Conference on Circuits, Systems, Communications and Computers (CSCC 2015), Jul 2015, Zakynthos Island, Greece. Recent Advances in Circuits Proceedings of the 19th International Conference on Circuits (part of CSCC '15) Zakynthos Island, Greece July 16‐20, 2015, Recent Advances in Electrical Engineering Series, 51, pp.129-132, 2015. 〈in2p3-01179604〉

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