1-Grad total dose evaluation of 65 nm CMOS technology for the HL-LHC upgrades

M. Menouni 1 M. Barbero 1 F. Bompard 1 S. Bonacini D. Fougeron 1 R. Gaglione 2 A. Rozanov 1 P. Valerio A. Wang 1
1 CPPM - Centre de Physique des Particules de Marseille
2 LAPP/Laboratoire d'Annecy-le-Vieux de Physique des Particules - Laboratoire d'Annecy de Physique des Particules
Abstract : The radiation tolerance of 65 nm bulk CMOS devices was investigated using 10 keV X-rays up to a Total Ionizing Dose (TID) of 1 Grad. Irradiation tests were performed at room temperature (25°C) as well as at low temperature (−15°C). The implications on the DC performance of n and p channel transistors are presented. For small size devices, a strong performance degradation is observed from a dose of 100 Mrad. Irradiations made at room temperature up to 1 Grad show a complete drive loss in PMOS devices, due to decreasing transconductance. When the irradiation is conducted at −15°C, the devices show less radiation damage. Annealing helps recovering a small part of the drive capabilities of the small size devices, but the threshold voltage shift is still high and might compromise the operation in some digital applications.
Type de document :
Communication dans un congrès
Topical Workshop on Electronics for Particle Physics TWEPP 2014, Sep 2014, Aix en Provence, France. Journal of Instrumentation, 10 (05), pp.C05009, 2015, 〈10.1088/1748-0221/10/05/C05009〉
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Contributeur : Claudine Bombar <>
Soumis le : vendredi 21 août 2015 - 14:41:43
Dernière modification le : jeudi 18 janvier 2018 - 02:03:24

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M. Menouni, M. Barbero, F. Bompard, S. Bonacini, D. Fougeron, et al.. 1-Grad total dose evaluation of 65 nm CMOS technology for the HL-LHC upgrades. Topical Workshop on Electronics for Particle Physics TWEPP 2014, Sep 2014, Aix en Provence, France. Journal of Instrumentation, 10 (05), pp.C05009, 2015, 〈10.1088/1748-0221/10/05/C05009〉. 〈in2p3-01185762〉

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