Abstract : A cryogenic and low noise front end ASIC has been developed for WA105 experiment. Considering previous designs, the dynamic range had been multiplied by 6. In order to absorb high input charge and maintain low noise for small signals, we converged to a double slope functionality. The identical channel of this 16-channel chip is made of a low noise Charge Sensitive Amplifier (CSA) with a MOSCAP around 500fF and a 2MO feedback resistor. The CSA is followed by a line driver. The input referred noise level requires at least 1500 e- rms at -160°C with an input detector capacitance (Cdet) of 250pF. With such performance, the input signal range of 3fC to 1.2pC is attainable. This front end is implemented in standard 350nm CMOS process.
