Design of low power 12bit 40MSPS SAR ADCs with a redundancy algorithm and digital calibration for high dynamic range calorimeter readout

M. Zeloufi 1 D. Dzahini 1 F. Rarbi 1 L. Gallin-Martel 1 J. Bouvier 1
1 LPSC - Laboratoire de Physique Subatomique et de Cosmologie
Abstract : We present two SAR ADCs using a generalized redundant search algorithm and offering the flexibility to relax the requirements on the DAC settling time. Two more bits of redundancy allow also a digital calibration, based on a code density analysis to compensate the capacitors mismatching effects. A monotonic switching algorithm is used for these prototypes saving about 70% of dynamic power consumption compared to conventional switching algorithm. A fully differential was used for both prototypes featuring 12bit 40MS/s in a CMOS 130nm 1P8M process
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Poster
5th Common ATLAS CMS Electronic Workshop for LHC Upgrades (ACES 2016), Mar 2016, Geneva, Switzerland. 〈https://indico.cern.ch/event/468486/〉
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http://hal.in2p3.fr/in2p3-01292733
Contributeur : Emmanuelle Vernay <>
Soumis le : mercredi 23 mars 2016 - 16:25:28
Dernière modification le : mardi 22 mai 2018 - 21:48:10

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M. Zeloufi, D. Dzahini, F. Rarbi, L. Gallin-Martel, J. Bouvier. Design of low power 12bit 40MSPS SAR ADCs with a redundancy algorithm and digital calibration for high dynamic range calorimeter readout . 5th Common ATLAS CMS Electronic Workshop for LHC Upgrades (ACES 2016), Mar 2016, Geneva, Switzerland. 〈https://indico.cern.ch/event/468486/〉. 〈in2p3-01292733〉

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