GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards

Abstract : The high-energy physics experiments at the CERN's Large Hadron Collider (LHC) are preparing for Run3, which is foreseen to start in the year 2021. Data from the high radiation environment of the detector front-end electronics are transported to the data processing units, located in low radiation zones through GBT (Gigabit transceiver) links. The present work discusses the GBT link performance study carried out on custom FPGA boards, clock calibration logic and its implementation in new Arria 10 FPGA.
Type de document :
Communication dans un congrès
Topical Workshop on Electronics for Particle Physics (TWEPP2015), Sep 2015, Lisbonne, Portugal. Journal of Instrumentation (JINIST), 11 (03), pp.C03039 - C03039, 2016, 〈http://www.lip.pt/events/2015/TWEPP/〉. 〈10.1088/1748-0221/11/03/C03039〉
Liste complète des métadonnées

http://hal.in2p3.fr/in2p3-01451868
Contributeur : Danielle Cristofol <>
Soumis le : mercredi 1 février 2017 - 14:54:22
Dernière modification le : jeudi 18 janvier 2018 - 02:21:28

Lien texte intégral

Identifiants

Collections

Citation

J. Mitra, S. A. Khan, M.B. Marin, J.-P. Cachemiche, E. David, et al.. GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards. Topical Workshop on Electronics for Particle Physics (TWEPP2015), Sep 2015, Lisbonne, Portugal. Journal of Instrumentation (JINIST), 11 (03), pp.C03039 - C03039, 2016, 〈http://www.lip.pt/events/2015/TWEPP/〉. 〈10.1088/1748-0221/11/03/C03039〉. 〈in2p3-01451868〉

Partager

Métriques

Consultations de la notice

60