GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards

J. Mitra 1 S. A. Khan 1 M.B. Marin 2 J.-P. Cachemiche 3 E. David 4 F. Hachon 3 F. Rethore 3 T. Kiss 4 S. Baron 2 A. Kluge 2 T. K. Nayak 1
1 Variable Energy Cyclotron Centre
2 CERN [Genève]
3 CPPM - Centre de Physique des Particules de Marseille
4 Wigner Research Centre for Physics [Budapest]
Abstract : The high-energy physics experiments at the CERN's Large Hadron Collider (LHC) are preparing for Run3, which is foreseen to start in the year 2021. Data from the high radiation environment of the detector front-end electronics are transported to the data processing units, located in low radiation zones through GBT (Gigabit transceiver) links. The present work discusses the GBT link performance study carried out on custom FPGA boards, clock calibration logic and its implementation in new Arria 10 FPGA.
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Conference papers
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Contributor : Danielle Cristofol <>
Submitted on : Wednesday, February 1, 2017 - 2:54:22 PM
Last modification on : Friday, August 9, 2019 - 4:32:02 PM

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J. Mitra, S. A. Khan, M.B. Marin, J.-P. Cachemiche, E. David, et al.. GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards. Topical Workshop on Electronics for Particle Physics (TWEPP2015), Sep 2015, Lisbonne, Portugal. pp.C03039 - C03039, ⟨10.1088/1748-0221/11/03/C03039⟩. ⟨in2p3-01451868⟩

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