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Conference papers
GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards
J. Mitra
1
S. A. Khan
1
M.B. Marin
2
J.-P. Cachemiche
3
E. David
4
F. Hachon
3
F. Rethore
3
T. Kiss
4
S. Baron
2
A. Kluge
2
T. K. Nayak
1
2
CERN [Genève] (Route de Meyrin 385, 1217 Meyrin, Genève - Switzerland)
3
CPPM - Centre de Physique des Particules de Marseille (163, avenue de Luminy - Case 902 - 13288 Marseille cedex 09 - France)
- AMU - Aix Marseille Université : UMR7346 / UMR6550 / UMR6450 / URA6450 (Aix-Marseille Université Jardins du Pharo 58 Boulevard Charles Livon 13284 Marseille cedex 7 - France)
- IN2P3 - Institut National de Physique Nucléaire et de Physique des Particules du CNRS (France)
- CNRS - Centre National de la Recherche Scientifique : UMR7346 / UMR6550 / UMR6450 / URA6450 (France)
4
Wigner Research Centre for Physics [Budapest] (1121 Budapest
Konkoly-Thege Miklós út 29-33. - Hungary)
- MTA - Hungarian Academy of Sciences (Széchenyi István sqr. 9, 1051 Budapest - Hungary)
Abstract : The high-energy physics experiments at the CERN's Large Hadron Collider (LHC) are preparing for Run3, which is foreseen to start in the year 2021. Data from the high radiation environment of the detector front-end electronics are transported to the data processing units, located in low radiation zones through GBT (Gigabit transceiver) links. The present work discusses the GBT link performance study carried out on custom FPGA boards, clock calibration logic and its implementation in new Arria 10 FPGA.
Document type :
Conference papers
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http://hal.in2p3.fr/in2p3-01451868
Contributor : Danielle Cristofol Connect in order to contact the contributor
Submitted on : Wednesday, February 1, 2017 - 2:54:22 PM
Last modification on : Wednesday, November 3, 2021 - 7:27:02 AM
Contributor : Danielle Cristofol Connect in order to contact the contributor
Submitted on : Wednesday, February 1, 2017 - 2:54:22 PM
Last modification on : Wednesday, November 3, 2021 - 7:27:02 AM
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Identifiers
- HAL Id : in2p3-01451868, version 1
- DOI : 10.1088/1748-0221/11/03/C03039
Citation
J. Mitra, S. A. Khan, M.B. Marin, J.-P. Cachemiche, E. David, et al.. GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards. Topical Workshop on Electronics for Particle Physics (TWEPP2015), Sep 2015, Lisbonne, Portugal. pp.C03039 - C03039, ⟨10.1088/1748-0221/11/03/C03039⟩. ⟨in2p3-01451868⟩
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