GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards

J. Mitra; S. A. Khan; M.B. Marin; J.-P. Cachemiche; E. David; F. Hachon; F. Rethore; T. Kiss; S. Baron; A. Kluge; T. K. Nayak

GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards

J. Mitra ¹ S. A. Khan ¹ M.B. Marin ² J.-P. Cachemiche ³ E. David ⁴ F. Hachon ³ F. Rethore ³ T. Kiss ⁴ S. Baron ² A. Kluge ² T. K. Nayak ¹

1 Variable Energy Cyclotron Centre

2 CERN [Genève]

3 CPPM - Centre de Physique des Particules de Marseille

4 Wigner Research Center for Physics [Budapest]

Abstract : The high-energy physics experiments at the CERN's Large Hadron Collider (LHC) are preparing for Run3, which is foreseen to start in the year 2021. Data from the high radiation environment of the detector front-end electronics are transported to the data processing units, located in low radiation zones through GBT (Gigabit transceiver) links. The present work discusses the GBT link performance study carried out on custom FPGA boards, clock calibration logic and its implementation in new Arria 10 FPGA.

Document type :

Conference papers

Domain :

Engineering Sciences [physics] / Micro and nanotechnologies/Microelectronics

Complete list of metadatas

http://hal.in2p3.fr/in2p3-01451868
Contributor : Danielle Cristofol <>
Submitted on : Wednesday, February 1, 2017 - 2:54:22 PM
Last modification on : Thursday, January 18, 2018 - 2:21:28 AM

GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards

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GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards

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