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Pixel architectures in a HV-CMOS process for the ATLAS inner detector upgrade

Abstract : In this paper, design details and simulation results of new pixel architectures designed in LFoundry 150 nm high voltage CMOS process in the framework of the ATLAS high luminosity inner detector upgrade are presented. These pixels can be connected to the FE-I4 readout chip via bump bonding or glue and some of them can also be tested without a readout chip. Negative high voltage is applied to the high resistivity (> 2 kΩ .cm) substrate in order to deplete the deep n-well charge collection diode, ensuring good charge collection and radiation tolerance. In these pixels, the front-end has been implemented inside the diode using both NMOS and PMOS transistors. The pixel pitch is 50 μm × 250 μm for all pixels. These pixels have been implemented in a demonstrator chip called LFCPIX.
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Contributor : Danielle Cristofol Connect in order to contact the contributor
Submitted on : Tuesday, February 14, 2017 - 1:27:09 PM
Last modification on : Tuesday, March 30, 2021 - 3:18:18 AM




Y. Degerli, S. Godiot, F. Guilloux, T. Hemperek, H. Krüger, et al.. Pixel architectures in a HV-CMOS process for the ATLAS inner detector upgrade. Topical Workshop on Electronics for Particle Physics (TWEPP2016), Sep 2016, Karlsruhe, Germany. pp.C12064, ⟨10.1088/1748-0221/11/12/C12064⟩. ⟨in2p3-01467357⟩



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