Skip to Main content Skip to Navigation
Conference papers

An 8-bit, 100-MSPS fully dynamic SAR ADC for ultra-high speed image sensor

Abstract : In this paper, a dynamic and power efficient 8-bit and 100-MSPS Successive Approximation Register (SAR) Analog-to- Digital Converter (ADC) is presented. The circuit uses a nondifferential capacitive Digital-to-Analog (DAC) architecture segmented by 2. The prototype is produced in a commercial 65-nm 1P7M CMOS technology with 1.2-V supply voltage. The size of the core ADC is 208.6 x 103.6 μm2. The post-layout noise simulation results feature a SNR of 46.9 dB at Nyquist frequency, which means an effective number of bit (ENOB) of 7.5-b. The total power consumption of this SAR ADC is only 1.55 mW at 100-MSPS. It achieves then a figure of merit of 85.6 fJ/step.
Complete list of metadatas

http://hal.in2p3.fr/in2p3-01712999
Contributor : Emmanuelle Vernay <>
Submitted on : Tuesday, February 20, 2018 - 9:35:30 AM
Last modification on : Thursday, August 6, 2020 - 3:09:30 AM

Identifiers

  • HAL Id : in2p3-01712999, version 1

Citation

F. Rarbi, D. Dzahini, W. Uhring. An 8-bit, 100-MSPS fully dynamic SAR ADC for ultra-high speed image sensor . International Conference on Integrated Circuit Design and Technology (ICIDT 2018), Jan 2018, Paris, France. pp.1-6. ⟨in2p3-01712999⟩

Share

Metrics

Record views

93