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Topical Workshop on Electronics for Particle Physics - TWEPP-11, Vienna : Autriche (2011)
The FE-I4 pixel readout system-on-chip resubmission for the insertable B-Layer project
V. Zivkovic, J.D. Schipper, M. Garcia-Sciveres, A. Mekkaoui, M. Barbero, G. Darbo, D. Gnani, T. Hemperek, M. Menouni1, D. Fougeron1, F. Gensolen1, F. Jensen, L. Caminada, V. Gromov, R. Kluit, J. Fleury2, H. Kruger, M. Backhaus, X. Fang, L. Gonella, A. Rozanov1, D. Arutinov
ATLAS Collaboration(s)

The FE-I4 is a new pixel readout integrated circuit designed to meet the requirements of ATLAS experiment upgrades. The first samples of the FE-I4 engineering run (called FE-I4A) delivered promising results in terms of the requested performances. The FE-I4 team envisaged a number of modifications and fine-tuning before the actual exploitation, planned within the Insertable B-Layer (IBL) of ATLAS. As the IBL schedule was pushed significantly forward, a quick and efficient plan had to be devised for the FE-I4 redesign. This article will present the main objectives of the resubmission, together with the major changes that were a driving factor for this redesign. In addition, the top-level verification and test efforts of the FE-I4 will also be addressed.
1 :  CPPM - Centre de Physique des Particules de Marseille
2 :  LAL - Laboratoire de l'Accélérateur Linéaire
Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique