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SEU tolerant latches design for the ATLAS pixel readout chip
Menouni M., Rozanov A., Barbero M.-B., Gonella L., Hemperek T.
TWEPP 2012 Topical Workshop on Electronics for Particle Physics, Oxford : Royaume-Uni (2012) - http://hal.in2p3.fr/in2p3-00757585
Sciences de l'ingénieur/Electronique
Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique
SEU tolerant latches design for the ATLAS pixel readout chip
M. Menouni1, A. Rozanov1, M.-B. Barbero, L. Gonella, T. Hemperek
1 :  CPPM - Centre de Physique des Particules de Marseille
http://marwww.in2p3.fr/
CNRS : UMR7346 – IN2P3 – Université de la Méditerranée - Aix-Marseille II
163, avenue de Luminy - Case 902 - 13288 Marseille cedex 09
France
The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches where layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. For the future pixel readout design, a prototype chip containing 512 pixels is implemented in a 65 nm CMOS process. SEU tolerant latches are implemented for the pixel configuration and the SEU tolerance is under test and evaluation.

Communications sans actes
21/09/2012

TWEPP 2012 Topical Workshop on Electronics for Particle Physics
Oxford
Royaume-Uni
17/09/2012
21/09/2012
M. Menouni