HAL : in2p3-00479837, version 1

DOI : 10.1016/j.nima.2010.04.101

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7th International ""Hiroshima"" Symposium on the Development and Application of Semiconductor Tracking Detectors, Hiroshima : Japan (2009)

The FE-I4 Pixel Readout Integrated Circuit

M. Garcia-Sciveres, D. Arutinov, M. Barbero, R. Beccherle, S. Dube, D. Elledge, J. Fleury1, D. Fougeron2, F. Gensolen2, D. Gnani, V. Gromov, T. Hemperek, M. Karagounis, R. Kluit, A. Kruth, A. Mekkaoui, M. Menouni2, J.-D. Schipper

ATLAS Collaboration(s)

(2011)

A new pixel readout integrated circuit denominated FE-I4 is being designed to meet the requirements of ATLAS experiment upgrades. It will be the largest readout IC produced to date for particle physics applications, filling the maximum allowed reticle area. This will significantly reduce the cost of future hybrid pixel detectors. In addition, FE-I4 will have smaller pixels and higher rate capability than the present generation of LHC pixel detectors. Design features are described along with simulation and test results, including low power and high rate readout architecture, mixed signal design strategy, and yield hardening.

1 :	LAL - Laboratoire de l'Accélérateur Linéaire
2 :	CPPM - Centre de Physique des Particules de Marseille

Thème(s)

:

Sciences de l'ingénieur/Electronique Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique

Mot(s)-clé(s) : Pixel detector – ATLAS upgrades – High luminosity – 130 nm

in2p3-00479837, version 1

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Contributeur : Danielle Cristofol <>

Déposé pour le compte de : Mohsine Menouni <>

Soumis le : Lundi 3 Mai 2010, 08:30:04

Dernière modification le : Vendredi 24 Juin 2011, 14:54:06