724 articles – 3377 Notices  [english version]
HAL : in2p3-00612913, version 1

Fiche détaillée  Récupérer au format
International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design and IEEE 2011 ADC Forum, Ovieto : Italie (2011)
Hardware Implementation of an ADC Error Compensation Using Neural Networks
Hélène Chanal1

A compensation technique for Analog-to-Digital Converter (ADC) based on a neural network is proposed. The implementation is done both in software and in a hardware description language. The latter is targeted for a massively parallel ASIC. The training of the neural network is done by learning a Look Up Table generated by processing the output of the ADC for sine waves inputs. Then, the effective number of bits (ENOB) is computed over a large range of frequencies for the raw data of a 100MS/s ADC and for the compensated data. These results are used to compare various neural network architecture and the effects of the approximations made for the hardware implementation.
1 :  LPC - Laboratoire de Physique Corpusculaire [Clermont-Ferrand]
Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique