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Publications du LPC-CLERMONT |  |
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Publications du LPC-CLERMONT | |
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| HAL : in2p3-00612913, version 1 |
| Fiche détaillée |  Récupérer au format |
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| International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design and IEEE 2011 ADC Forum, Ovieto : Italie (2011) |
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| Hardware Implementation of an ADC Error Compensation Using Neural Networks |
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| H. Chanal1 |
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| (2011) |
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| A compensation technique for Analog-to-Digital Converter (ADC) based on a neural network is proposed. The implementation is done both in software and in a hardware description language. The latter is targeted for a massively parallel ASIC. The training of the neural network is done by learning a Look Up Table generated by processing the output of the ADC for sine waves inputs. Then, the effective number of bits (ENOB) is computed over a large range of frequencies for the raw data of a 100MS/s ADC and for the compensated data. These results are used to compare various neural network architecture and the effects of the approximations made for the hardware implementation. |
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| 1 : | LPC-CLERMONT - Laboratoire de Physique Corpusculaire de Clermont-Ferrand |
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| Thème(s) | : | Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique |
| in2p3-00612913, version 1 | |
| http://hal.in2p3.fr/in2p3-00612913 | |
| oai:hal.in2p3.fr:in2p3-00612913 | |
| Contributeur : Jeanine Pellet | |
| Soumis le : Lundi 1 Août 2011, 15:10:04 | |
| Dernière modification le : Mardi 2 Août 2011, 10:32:38 | |
