Design and performances of a compensated mean-timer - IN2P3 - Institut national de physique nucléaire et de physique des particules Access content directly
Conference Papers IEEE Transactions on Nuclear Science Year : 2000

Design and performances of a compensated mean-timer


An integrated mean-timer has been designed. This circuit integrates a compensation system in order to minimize thermal drift and process variations. This circuit designed in BiCMOS 0.8 mu m integrates input and output ECL translators. The drift cancellation system is based on a regulated delay line controlled by a PLL. The PLL circuit can be disconnected and an external control voltage can be used. The circuit can also run without any cancellation system. In the last part, a sub-delay resolution system is discussed.
No file

Dates and versions

in2p3-00005874 , version 1 (24-08-2000)


  • HAL Id : in2p3-00005874 , version 1


Daniel Dzahini, J. Pouxe, O. Rossetto. Design and performances of a compensated mean-timer. IEEE 1999 Nuclear Science Symposium and Medical Imaging Conference, Oct 1999, Seattle, United States. pp.839-843. ⟨in2p3-00005874⟩
8 View
0 Download


Gmail Facebook X LinkedIn More