A new ATLAS pixel chip FE-I4 has been developed for use in upgraded LHC luminosity environments, including the near-term Insertable B-Layer upgrade. FE-I4 is designed in a 130 nm CMOS technology, presenting advantages in terms of radiation tolerance and digital logic density compared to the 0.25 μm CMOS technology used for the current ATLAS pixel IC, FE-I3. FE-I4 architecture is based on an array of 80×336 pixels, each 50×250 μm2, consisting of analog and digital sections. The analog pixel section is designed for low power consumption and compatibility to several sensor candidates. It is based on a two-stage architecture with a pre-amp AC-coupled to a second stage of amplification. It features leakage current compensation circuitry, local 4-bit pre-amp feedback tuning and a discriminator locally adjusted through 5 configuration bits. The digital architecture is based on a 4-pixel unit called Pixel Digital Region (PDR) allowing for local storage of hits in 5-deep data buffers at pixel level for the duration of the first level trigger latency (L1T). This local storage helps overcoming the limitations of the current ATLAS pixel chip FE-I3 at high hit rates. The PDR-based digital architecture allows for a power-efficient, low recording inefficiency design and reduces the problem of time-walk. The chip periphery consists of a command decoder unit which handles the programming of DACs and registers as well as the decoding of L1T requests, a control block which organizes data output from the pixel array and provides data formatting, various powering blocks, an 8b10b coder and a clock multiplier unit which enables data transmission at 160 Mb/s through pseudo-LVDS transmitters. Increased power consumption in the inner layers of ATLAS translates into more material for cooling and power routing, which degrades the tracking and the b-tagging quality. The FE-I4 collaboration hence places severe constraints on the power consumption of all blocks.