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SEU tolerant memory design for the ATLAS pixel readout chip

Abstract : The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. To prepare for the new pixel readout chip planned for the future upgrades, a prototype chip containing 512 pixels has been designed in a 65 nm CMOS process and a new approach is adopted for SEU tolerant latches. Results in terms of SEU and TID tolerance are presented.
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Contributor : Danielle Cristofol Connect in order to contact the contributor
Submitted on : Wednesday, March 13, 2013 - 2:50:57 PM
Last modification on : Tuesday, October 19, 2021 - 11:00:04 PM

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M. Menouni, D. Arutinov, M. Backhaus, M. Barbero, R. Beccherle, et al.. SEU tolerant memory design for the ATLAS pixel readout chip. Topical Workshop on Electronics for Particle Physics 2012 (TWEPP12), Sep 2012, Oxford, United Kingdom. pp.C02026, ⟨10.1088/1748-0221/8/02/C02026⟩. ⟨in2p3-00800250⟩



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