A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors - IN2P3 - Institut national de physique nucléaire et de physique des particules Access content directly
Journal Articles Journal of Instrumentation Year : 2008

A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors

Abstract

A 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35µm CMOS technology. A non-resetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of a 2.5 bit pipeline stage followed by a 2 bit flash stage. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1µs. The size for the layout is 80µm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20µm wide.
Fichier principal
Vignette du fichier
ADC_DS_4b.pdf (753.93 Ko) Télécharger le fichier
Origin Files produced by the author(s)

Dates and versions

in2p3-00203112 , version 1 (09-01-2008)

Identifiers

Cite

M. Dahoumane, Daniel Dzahini, J. Bouvier, E. Lagorio, L. Gallin-Martel, et al.. A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors. Journal of Instrumentation, 2008, 3, p03002. ⟨10.1088/1748-0221/3/03/P03002⟩. ⟨in2p3-00203112⟩
28 View
164 Download

Altmetric

Share

Gmail Mastodon Facebook X LinkedIn More